The present invention relates to the formation of metal interconnection layers during the manufacture of semiconductor devices, and more particularly to the formation of a damascene structure in a metal interconnect region.
The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising 5 or more levels of metalization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnect pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading, and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with sub-micron design rules, e.g., a design rule of about 0.18xcexc and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
In prior technologies, aluminum was used in very large scale integration interconnect metalizations. Copper and copper alloys have received considerable attention as a candidate for replacing aluminum in these metalizations. Copper has a lower resistivity than aluminum and improved electrical properties vis-à-vis tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring.
In the formation of a dual damascene structure, a conductive line and vias that connect the line to conductive elements in a previously formed underlying conductive interconnect layer, are simultaneously deposited. The conductive material is deposited into openings (e.g., via holes and trenches) created in dielectric material that overlays the conductive interconnect layer. Typically, a first layer of dielectric material is deposited over a bottom etch stop layer that covers and protects the conductive interconnect layer. A middle etch stop layer is then deposited over the first dielectric layer, followed by deposition of a second dielectric layer. A via hole is then etched through the second dielectric layer, the middle etch stop layer, and the second dielectric layer. A trench is then etched in the second dielectric layer. The trench at least partially overlaps the via hole. The etching of the trench thus stops at the middle stop layer. The bottom etch stop layer within the via hole, which has protected the conductive material in the conductive interconnect layer, is then removed with a different etchant chemistry. With the via holes now formed in the first dielectric layer and a trench formed in the second dielectric layer, conductive material is simultaneously deposited in the via and the trench in a single deposition step. (If copper is used as the conductive material, a barrier layer is conventionally deposited first, to prevent copper diffusion.) The conductive material makes electrically conductive contact with the conductive material in the underlying conductive interconnect layer.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher k values. Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, the low k materials, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, and the material sold under the trade name of FLARE, are often more difficult to handle than traditionally employed higher k materials, such as an oxide.
When forming a dual damascene structure in which a low k dielectric material, such as BCB, is substituted for higher k dielectric materials in the two dielectric layers in which the vias and the trench are created, the problem of xe2x80x9cundercuttingxe2x80x9d becomes a concern. Undercutting is the undesired enlargement of the via hole in the first dielectric layer, under the middle etch stop layer, during the etching of the trench in the second dielectric layer. The undercutting occurs since the low k dielectric material in the first dielectric layer reacts to the etchant when it is applied to the low k dielectric material in the second dielectric layer. The first dielectric layer is somewhat protected by the middle stop layer, but the etchant still often undercuts the first dielectric layer underneath the middle stop layer. The undercutting causes the ultimately formed via structure to be incorrectly shaped.
The nitride etch stop layer increases the overall k value of the film, since it remains in place in the final product. Nitride has a relatively high k value, especially compared with low k materials. Hence, the sought for reduction in the overall k value gained by the use of low k dielectric materials in the dielectric layers of dual damascene arrangement is offset somewhat by the higher k value of the nitride etch stop layer.
There is a need for a method and arrangement that provides a film with a lower overall dielectric constant value that will exhibit improved overall performance, yet avoids the undercutting that occurs with the use of a low k dielectric material in the dielectric layers of a dual damascene interconnect arrangement, and at the same time reduces the contribution to a higher overall k value introduced by a nitride etch stop layer between the dielectric layers.
This and other needs are met by the present invention which provides a method of forming an opening in dielectric interconnect layers by forming a first dielectric layer over a conductive layer. The first dielectric layer comprises a first low k dielectric material. A second dielectric layer is formed on the first dielectric layer and comprises a second low k dielectric material having different etch sensitivity than the first low dielectric material to at least one etchant chemistry. A first opening is etched through the first dielectric layer. A second opening is then etched in the second dielectric layer, the second opening at least partially overlapping the first opening.
The earlier stated needs are met by another embodiment of the present invention that provides a dual damascene arrangement having a conductive layer and a first dielectric layer over the conductive layer. The first dielectric layer comprises a first low k dielectric material. A second dielectric layer is on the first dielectric layer and comprises a second low k dielectric material having different etch sensitivity than the first low k dielectric material to at least one etchant chemistry. A first opening extends through the first dielectric layer to the conductive layer. A second opening extends through the second dielectric layer to the conductive layer. Conductive material fills the first and second openings.
The use of different low k materials in the respective dielectric layers of a dual damascene arrangement that are selected to have different etch sensitivity to at least one etchant chemistry, in accordance with embodiments of the present invention, allows one dielectric layer to be etched without further etching of the other dielectric layer during a dual dielectric formation process. This also allows the elimination of an etch stop layer formed of a higher k value material, such as oxide or nitride. The elimination of the etch stop layer reduces the overall k value of the film and thereby increases the operating speed of the chip.